The Advanced/ZP baseboard provides four 72-pin SIMM sites for memory expansion. The sockets support 1M x 32 (4 MB), 2M x 32 (8 MB), 4M x 32 (16 MB), and 8M x 32 (32 MB) single-sided or double-sided SIMM modules. Minimum memory size is 8 MB and maximum memory size, using four 8M x 32 SIMM modules, is 128 MB. For external CPU speeds of less than 60 Mhz (used with 75, 90 and 120 Mhz processors) memory timing requires 70 ns fast page devices or, for higher performance, 70 ns EDO DRAM. For external CPU speeds of 66 Mhz (used with 100 Mhz processors) you must use 60 nS EDO DRAM, but 70 nS fast page DRAM may still be used. Parity generation and checking is not supported by the chip set.

The four sockets are arranged as Bank 0 and Bank 1, with each bank consisting of two sockets and providing a 64-bit wide data path. Both SIMMs in a bank must be of the same memory size and type, however Banks 0 and 1 may have different types of memory installed. It is even possible to have 70 ns Fast Page DRAM in one bank and 60 ns EDO DRAM in the other, in which case each bank is independently optimized for maximum performance. Bank 0 only, Bank 1 only, or both banks may be populated. There are no jumper settings required for the memory size or type, which is automatically detected by the system BIOS. Tin lead SIMMs are required to be used when adding Fast Page or EDO DRAM.

EDO DRAM

Extended Data Out (or Hyper Page Mode) DRAM is designed to improve the DRAM read performance. EDO DRAM holds the memory data valid until the next CAS# falling edge, unlike standard fast page mode DRAM which tri-states the memory data when CAS# negates to precharge for the next cycle. With EDO, the CAS# precharge overlaps the data valid time, allowing CAS# to negate earlier while still satisfying the memory data valid window time.

EXPANSION SLOTS

Up to six expansion slots may be populated on the Advanced/ZP baseboard. There are four ISA bus expansion conectors and three PCI expansion connectors. One slot is shared by connectors that will accommodate either an ISA or a PCI expansion card, but not both at the same time. This accounts for the disparity between the number of slots and connectors. All three PCI expansion slots accept PCI bus mastering cards, and fully comply with the PCI 2.10 specification. Three of the ISA slots and one PCI slot can accommodate full length add-in cards. Interference with the processor heat sink and CPU voltage regulator support circuitry limits the rest of the ISA and PCI slots to being able to support only half-length add-in cards.

PCI 3.3 VOLT CAPABILITIES

To maintain strict compliance with the PCI specification, the baseboard provides a connector which can be used to route 3.3 volt power to the PCI slots. The connector may be used with a separate 3.3 volt power supply or with a custom designed voltage converter. Note: The on-board 3.3 volt regulator provides power for the CPU, PCIset and L2 cache only, not the PCI slots.

PERIPHERAL COMPONENT INTERCONNECT (PCI) PCISET

The Intel Triton 82430FX PCIset consists of the 82437FX Triton System Controller (TSC), two 82438FX Triton Data Path (TDP) devices, and one 82371FB PCI ISA/IDE Accelerator (PIIX) bridge chip. The Triton PCIset provides the following functions:

CPU interface control
Integrated L2 write-back cache controller
- Pipelined Burst or standard SRAM
- 256kB or 512kB Direct Mapped
- Integrated Tag Status Bits
Integrated DRAM controller
- 64-bit path to Memory
- Support for EDO and Fast Page DRAM
- 4 MB to 128 MB main memory
Fully synchronous PCI bus interface
- 25/30/33 MHz
- PCI to DRAM > 100 Mbytes/sec
- PCI to DRAM posting of 12 Dwords
- 5 Dword buffers for CPU-PCI write posting
- 4 Dword buffers for PCI to Memory bus master cycles
- Support for up to 5 PCI masters
Interface between the PCI bus and ISA bus
Integrated fast IDE interface
- Support for up to 4 devices
- PIO Mode 4 transfers up to 16MB/sec
- Integrated 8 x 32-bit buffer for PCI IDE burst transfers
Enhanced Fast DMA controller
Interrupt controller and steering
Counters/Timers
SMI interrupt logic and timer with Fast On/Off mode

82437FX TRITON SYSTEM CONTROLLER (TSC)

The 82437FX provides all control signals necessary to drive a second level cache and the DRAM array, including multiplexed address signals. It also controls system access to memory and generates snoop controls to maintain cache coherency. The TSC comes in a 208 pin QFP package.

82438FX TRITON DATA PATH (TDP)

There are two 82438FX components which provide data bus buffering and dual port buffering to the memory array. Controlled by the 82437FX, the 82438FX devices add one load each to the PCI bus and perform all the necessary byte and word swapping required. Memory and I/O write buffers are included in these devices. The TDP devices are 100 pin QFP packages.

82371FB PCI ISA/IDE ACCELERATOR (PIIX)

The 82371FB provides the interface between the PCI and ISA buses and integrates a dual channel fast IDE interface capable of supporting up to 4 devices, seven 32-bit DMA channels, five 16-bit timer/counters, two eight-channel interrupt controllers, PCI-to-AT interrupt mapping circuitry, NMI logic, ISA refresh address generation, and PCI/ISA bus arbitration circuitry. The PIIX comes in a 208-pin QFP package.

TRITON DESIGN CONSIDERATIONS

Triton Memory Hole Limitation

Due the design of the Triton chipset, only one memory hole can be active at a time. The user can not set the Base Memory size to 512 KB and enable the ISA LFB at the same time.

Triton PCI Hold Time Requirement

The Triton chipset provides less hold time than the earlier Neptune and Mercury chipsets on the PCI address and data lines, but still is within the PCI specification. (The PCI specification calls out a 0 ns minimum hold time.) Some PCI expansion cards do not meet this requirement, and in fact require more hold time than the Triton chipset provides. Disabling PCI write bursting will sometimes enable these cards to function.

IDE SUPPORT

The Advanced/ZP baseboard provides two independent high performance bus-mastering PCI IDE interfaces capable of supporting PIO Mode 3 and Mode 4 devices for up to 16 MB/sec transfers. Support for ATAPI devices is provided in the system BIOS. The system BIOS also supports Logical Block Addressing (LBA) and ECHS on both IDE interfaces. When used in conjunction with a special driver the IDE interface operates as a PCI bus master for optimum performance in a multi-tasking environment. One such driver is provided by Intel for the Windows 95 environment.

NATIONAL SEMICONDUCTOR 87306 SUPER I/O CONTROLLER

Control for the integrated serial ports, parallel port, floppy drive, RTC and keyboard controller is incorporated into a single component, the National Semiconductor 87306. This component provides:

Two NS16C550-compatible UARTs with send/receive 16 byte FIFO - Support for an IrDA compliant Infra Red interface Multi-mode bi-directional parallel port - Standard mode; IBM and Centronics compatible - Enhanced Parallel Port (EPP) with BIOS/Driver support - High Speed mode; Enhanced Capabilities Port (ECP) compatible Industry standard floppy controller with 16 byte data FIFO (2.88 MB floppy support) Integrated Real Time Clock accurate within +/- 13 minutes/yr Integrated 8042 compatible keyboard controller

Configuration of these interfaces is possible via the CMOS Setup program that can be invoked during boot-up. The serial ports can be enabled as COM1, COM2 or disabled. COM2 can alternately be configured as an IRDA port. The parallel port can be configured as normal, extended , or disabled. The floppy interface can be configured for 720 KB, 1.2 MB, 1.44 MB, or 2.88 MB media. Header pins located near the back of the board allow cabling to use these interfaces.

KEYBOARD INTERFACE

The AT keyboard connector is located on the back panel side of the baseboard. The 5V lines to this connector is protected with a PolySwitch* circuit which acts much like a self-healing fuse, re-establishing the connection after an over-current condition is removed. While this device eliminates the possibility of having to replace a fuse, care should be taken to turn off the system power before installing or removing a keyboard.

The integrated 8042 microcontroller contains the AMI Megakey keyboard controller code which, besides providing traditional keyboard control functions, supports Power-On/Reset (POR) password protection. The POR password can be defined by the user via the Setup program. The keyboard controller also provides for the following "hot key" sequences:

· CTRL-ALT-DEL: System software reset. This sequence performs a software reset of the system by jumping to the beginning of the BIOS code and running the POST operation.

· CTRL-ALT+ and CTRL-ALT-: Turbo mode selection. CTRL-ALT- sets the system for de-turbo mode, emulating a 25 MHz AT, and CTRL-ALT+ sets the system for turbo mode. Changing the Turbo mode may be prohibited by an operating system, or when the CPU is in Protected mode or virtual 86 mode under DOS.

· CTRL-ALT-<defined in setup>: Power down and coffee-break key sequences take advantage of the SMM features of the Pentium processor to greatly reduce the system's power consumption while maintaining the responsiveness necessary to service external interrupts.

REAL TIME CLOCK, CMOS RAM AND BATTERY

The integrated Real Time Clock, RTC, is accurate to within 13 minutes/year. The RTC can be set via the BIOS SETUP Program. CMOS memory supports the standard 128­byte battery­backed RAM, fourteen bytes for clock and control registers, and 114 bytes of general purpose non-volatile CMOS RAM. All CMOS RAM is reserved for BIOS use. The CMOS RAM can be set to specific values or cleared to the system default values using the BIOS SETUP program. Also, the CMOS RAM values can be cleared to the system defaults by using a configuration switch on the baseboard. Appendix B lists switch and jumper configurations.

An external coin-cell style battery provides power to the RTC and CMOS memory. The battery has an estimated lifetime of seven years and is socketed for easy replacement. Refer to Appendix A for battery replacement details.

IRDA (INFRARED) SUPPORT

Serial port 2 can be configured to support an IrDA module via a 5 pin header connector. Once configured for IrDA, the user can transfer files to/from portable devices such as laptops, PDA's and printers using application software such as LapLink. The IrDA specification provides for data transfers at up to 115kbps from a distance of 1 meter.

A 5-pin header is provided to allow connection to a Hewlett Packard HSDSL-1000 compatible Infra-red transmitter/receiver.

SYSTEM BIOS

The Advanced/ZP baseboard uses an American Megatrends Incorporated (AMI) Pentium Processor ROM BIOS, which is stored in Flash EEPROM and easily upgraded using a floppy disk-based program. In addition to the AMIBIOS, the Flash EEPROM also contains the Setup utility, Power-On Self Tests (POST), update recovery code, and the PCI auto-configuration utility. This baseboard supports system BIOS shadowing, allowing the BIOS to execute from 32-bit on-board write-protected DRAM.

The BIOS displays a sign-on message during POST identifying the type of BIOS and a five-digit revision code. As an example the BIOS for the Advanced/ZE will be 1.00.02.BS0. As BIOS updates occur the revision number will increase to 1.00.03.BS0, and so on.

Information on BIOS functions can be found in the IBM PS/2 and Personal Computer BIOS Technical Reference published by IBM, and the ISA and EISA Hi-Flex AMIBIOS Technical Reference published by AMI. Both manuals are available at most technical bookstores.

FLASH IMPLEMENTATION

The Intel 28F001BXT 1 Mb FLASH component is organized as 128K x 8 (128 KB). The Flash device is divided into five areas, as described in Table 1.

The FLASH device resides in system memory in two 64 KB segments starting at E0000H, and can be mapped two different ways, depending on the mode of operation. In Normal Mode, address line A16 is inverted, setting the E000H and F000H segments so that the BIOS is organized as shown in the system address column above. Recovery mode removes the inversion on address line A16, swapping the E000H and F000H segments so that the 8 KB boot block resides at FE000H where the CPU expects the bootstrap loader to exist. This mode is only necessary in the unlikely event that a BIOS upgrade procedure is interrupted, causing the BIOS area to be left in an unusable state. For information on recovering the BIOS in the event of a catastrophic failure, refer to the appendix.

BIOS UPGRADES

FLASH memory makes distributing BIOS upgrades easy. A new version of the BIOS can be installed from a diskette. BIOS upgrades will be available as downloadable files on the Intel bulletin board.

The disk-based Flash upgrade utility, FMUP.EXE, has three options for BIOS upgrades:

The Flash BIOS can be updated from a file on a disk;

The current BIOS code can be copied from the Flash EEPROM to a disk file as a backup in the event that an upgrade cannot be successfully completed; or

The BIOS in the Flash device can be compared with a disk file to ensure the system has the correct BIOS version.

The upgrade utility ensures the upgrade BIOS extension matches the target system to prevent accidentally installing a BIOS for a different type of system. A recovery jumper is provided to allow recovery in the unlikely event of an unsuccessful BIOS upgrade. The jumper forces the ROM decode to access a 8 KB block of write protected recovery code in the Flash device.

SETUP UTILITY

The ROM-based Setup utility allows the configuration to be modified without opening the system for most basic changes. The Setup utility is accessible only during the Power-On Self Test, POST, by pressing the <F1> key after the POST memory test has begun and before boot begins. A prompt may be enabled that informs the user to press the <F1> key to access Setup. A switch on the baseboard can be set to prevent user access to Setup for security purposes. Setup options are detailed in the BIOS appendix.

PCI AUTO-CONFIGURATION

The PCI auto-configuration utility operates in conjunction with the system Setup utility to allow the insertion and removal of PCI cards to the system without user intervention. When the system is turned on after adding a PCI add-in card, the BIOS automatically configures interrupts, DMA channels, I/O space, and other parameters. The user does not have to configure jumpers or worry about potential resource conflicts. Because PCI cards use the same interrupt resources as ISA cards, the user must specify the interrupts used by ISA add-in cards in the Setup utility. The PCI Auto-Configuration function complies with version 2.10 of the PCI BIOS specification.

ISA PLUG & PLAY

The BIOS incorporates ISA Plug and Play capabilities conforming to version 1.0a of the Plug-n-Play specification. This will allow auto-configuration of Plug and Play ISA cards, and resource management for legacy ISA cards, when used in conjunction with the ISA Configuration Utility (ICU).

SHADOW MEMORY

Memory from C8000-DFFFF is not shadowed. This is a change from previous Intel products using AMI BIOS. This may have a slight adverse affect on the performance of some non-Plug and Play ISA cards. All or part of this area may be used as shared ISA memory if needed. Video BIOS located from C0000-C7FFF is shadowed to boost performance.

POWER MANAGEMENT

The Advanced/ZP will enable you to have an Energy Star compliant system through its Advanced Power Management resources. The Advanced/ZP BIOS supports power management via System Management Mode (SMM) interrupts to the CPU and Advanced Power Management (APM v1.1). In general, power management capabilities will allow the system to be put into a power managed Stand By state. This can be accomplished by pressing the sleep/resume button on the front of the chassis, entering an user configured hot-key sequence on the keyboard, or by the expiration of a hardware timer which detects system inactivity for a user-configurable length of time. While in the Stand By state, the Advanced/ZP baseboard reduces the system power consumption to Energy Star levels by utilizing the power saving capabilities of the Pentium®Processor, spinning down the IDE hard drive, and turning off an Energy Star rated monitor. Add-in cards supplied with APM-aware drivers can also be put into a power managed state for further energy savings. The ability to respond to external interrupts is fully maintained while in Stand By mode allowing the system to service requests such as in-coming FAX's or network messages while unattended.

FLASH LOGO AREA

Advanced/ZP supports a 4 KB programmable FLASH user area located at EC000-ECFFF. An OEM may use this area to display a custom logo. The BIOS accesses the user area at several points during the boot up sequence.

SECURITY FEATURES

ADMINISTRATIVE PASSWORD

The administrative password protects several sensitive Setup options from being viewable to a user unless the password is entered. These sensitive fields are viewable unless the administrative password is set.

BIOS PASSWORD

A BIOS password feature provides security during the boot process. A password can be entered using the Setup utility, and will be required on boot up before normal operation of the system can commence. To enable, disable, or change the password, refer to the Setup program options in the appendix.

If the password is forgotten, it can be cleared by turning off the system and setting the "password clear" jumper to the clear position.

SETUP ENABLE SWITCH

A baseboard configuration switch controls access to the BIOS Setup utility. By setting switch SW5 to the ON position, the user is prevented from accessing the Setup utility during the Power-On Self Test or at any other time. The message prompting the user to press <F1> to enter setup is also disabled

CONNECTORS

FRONT PANEL CONNECTIONS

The Advanced/ZP baseboard provides header connectors to support functions typically located on the chassis bezel:

• System Reset
• Power LED
• Keyboard Lock
• Hard Drive activity LED
• Turbo LED
• System Speaker
• Secondary CPU Fan
• Infra-Red (IrDA) port
• Sleep/Resume

Figure 3. Front Panel Connectors

Sleep/Resume

This two pin header, when connected to a momentary switch, can be used to put the system into a power managed state (standby) that will reduce the system's power consumption. If the system is in Stand By mode and the switch is pressed, the system will instantly "wake up" or Resume full system activity. When used with a power supply with a high efficiency rating, the Advanced/ZE is easily capable of reducing the system power to below EPA Energy Star requirements. The function of the Sleep/Resume button can also be achieved via the keyboard with a hot key sequence programmable in setup.

Infra-Red (IrDA) connector

Serial port 2 can be configured to support an IrDA module via a 5 pin header connector. Once configured for IrDA, the user can transfer files to/from portable devices such as laptops, PDA's and printers using application software such as LapLink. The IrDA specification provides for data transfers at up to 115kbps from a distance of 1 meter.

Speaker

The external speaker provides error beep code information during the Power-On Self Test if the system cannot use the video interface. See the appendix for more information about error beep codes.

BACK PANEL CONNECTIONS

The back panel provides external access to an AT style keyboard connector integrated on the Advanced/ZP baseboard. Figure 4 shows the general location of the AT style keyboard connector.

I/O CONNECTIONS

The baseboard contains shroudless stake pin header connections for cabling the serial, parallel, floppy, and IDE interfaces. Figure 5 shows the locations of these connectors and the orientation of pin 1 on each.

POWER CONSUMPTION

Table 2 lists the current used by system resources in a configuration which includes 8 MB of DRAM. Table 3 lists the typical power consumed by the same configuration. Note that the 3.3 volts used to drive the CPU and core logic is derived from an on-board voltage regulator from the +5 volt source. This information is provided only as a guide for calculating approximate total system power usage with additional resources added.

CURRENT

WATTS